Systems are known for grading integrated circuit components in wafer form by testing the same and applying a grading mark thereto. Reference is made to U.S. applications Ser. Nos. 436,844; and 436,845, each filed Jan. 28, 1974 and assigned to the assignee of this application.
In the current art of electronic circuits, integrated circuits or micro-circuits are fabricated in such a manner that thin semiconductor slices having a multiplicity of individual matrices or micro-circuits are formed. In the usual practice in the art, the slices contain multiple identical repeating matrices of the same type of micro-circuit or integrated circuit unit. The individual unit is sometimes referred to as an integrated circuit chip.
The present practice is to test each of the circuits of each integrated circuit chip formed on the semiconductor wafer prior to separating the wafer into the desired individual integrated circuit components. In some instances, the individual integrated circuit unit may contain multiple circuits, and it is therefore deisrable to test each of the circuits of the integrated circuit unit before the wafer is cut into individual integrated circuit units.
Since each micro-circuit of each wafer is normally in a predetermined precise relationship with respect to the adjacent circuit units, it is possible to test the circuitry if a probe can be accurately located on each preselected point corresponding to the circuit to be tested. It is possible, for example, to test several different circuits at the same time, or the same circuit of several different integrated circuit units.
Obviously, the positioning of the probes must be quite accurate and adjustable such that different integrated circuit units may be tested. Once the probes have been properly oriented, the wafer may be stepped from position to position so that each micro-circuit is properly located relative to the cooperative probe units for appropriate testing.
The orientation in a predetermined position may be defined as a precise location referenced by XY coordinates, and a vertical position defined by a Z coordinate. Since the wafer is generally planar, the proper vertical position of the probes used in testing must be closely controlled in order to obtain uniform contact pressure between each probe tip and each circuit.
The usual procedure involves placing the matrix on a work table which is movable vertically and rotatable. Normally the matrices are arranged such that the individual chips are disposed in a checkerboard pattern sometimes referred to as a "street and avenue" orientation. Accordingly it is necessary to rotate the matrix such that the streets and avenues are in the proper x-y orientation since the testing and grading involves a stepping sequence from one position defined by an x-y coordinate to another position defined by another x-y coordinate such that the proper circuit component is accurately aligned in each successive coordinate position.
Thus, the operator examines the matrix by an optical means and rotates the work table to bring the streets and avenues of the matrix into the proper x-y orientation. Thereafter, stepping from one x-y position to the next is carried out by automatic control means well known in the art.
Once the matrix is properly oriented in the x-y direction, the test probe arms are adjusted, as described in the above-identified applications, to position the tip thereof in the proper x-y-z position for testing a particular circuit component of a specific chip. After orientation of the probe arm, the table and the matrix is raised vertically such that the tip of the test probe contacts the circuit and the circuit tested. Thereafter the circuit is graded and the sequence repeated, i.e., the matrix is moved downwardly, indexed to the next x-y position and moved vertically such that the tip of the text arm contacts the next chip at the proper circuit being tested. In this manner the entire matrix is tested and graded. When a second identical matrix is placed on the platform all that need be done is to provide the proper x-y orientation and the next matrix is ready for testing and grading.
The above procedure, as will be apparent, requires extremely accurate location and positive control of the positioning of the matrix and the chips making up the matrix. One of the difficulties of the prior art devices has been the vertical movement of the platform in that the vertical position thereof is quite important in an automatic testing sequence.
For example, if the table overtravels in moving upwards, either the probe arms or the matrix or both may be damaged. The result is improper testing and grading. Another problem which is encountered is what is termed "bouncing" in that the platform tends to hunt for the final vertical position. When this takes place, the probe arm may scratch the matrix causing damage to an otherwise usable circuit.
Finally some of the problems cooperation prior devices stems from the fact that the vertical orientation of the platform in the raised position may vary for each vertical cycle of platform movement. When this takes place the contact pressure between the probe arm and the circuit varies from one test to another resulting in erroneous test data and possible incorrect grading of acceptable circuit components.
It accordingly becomes apparent that a need exists for a chuck assembly which accurately positions a work platform in a precise vertical position and which can operate rapidly and effectively without any bouncing or hunting as the platform reaches the predetermined vertical position.
Additionally, there are advantages in providing such a chuck assembly in which the plane of the work table is maintained in a true perpendicular position regardless of the rotational orientation of the work table. In this way, the work platform is "square" with a reference axis.
It is also advantageous to provide a motor drive system which so controls movement of the platform as to prevent hunting and bouncing while offering positive control of platform vertical position.